1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory and, more particularly, to a read circuit of a nonvolatile semiconductor memory of two-stage sense system using a level shift circuit and a single-ended sense amplifier.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing a conventional read circuit in an EPROM (Ultra-violet Erasable/Programmable Read-Only Memory). This circuit is basically the same as a circuit described by M. A. Van Buskirk et al., "A 200 ns 256K HMOSII EPROM" 1983 ISSCC DIGEST OF TECHNICAL PAPERS, pp. 162-163, p. 301 or M. A. Van Buskirk et al., "EPROMs graduate to 256-K density with scaled n-channel process" Electronics/Feb. 24, 1983, pp. 89-93. For the sake of descriptive convenience, the circuit is slightly modified.
In FIG. 1, reference symbols Vcc and Vss denote a power source potential (normally 5 V) and a ground potential, respectively. Reference numeral 1 denotes a memory cell (main memory cell) for holding and decreasing the potential of a bit line 2 in accordance with the content of stored data by discharging the potential; 3, a column selection enhancement N-channel transistor; 4, a bit line charge enhancement N-channel transistor; 5, a bit line transfer gate enhancement N-channel transistor; 6, a bias circuit; 7, a bit line load enhancement P-channel transistor having a gate and a drain connected to each other; 8, a sense line; 11, a dummy cell for discharging the potential of a dummy cell bit line 12 to decrease the potential; 13, a dummy column selection enhancement N-channel transistor; 14, a dummy cell bit line charge enhancement N-channel transistor; 15, a dummy cell bit line transfer gate enhancement N-channel transistor; 16, a dummy cell bias circuit; 17, a dummy cell bit line load enhancement P-channel transistor having a gate and a drain connected to each other; 18, a dummy cell sense line; and 20, a differential sense amplifier. The bias circuit 6 is used to apply a predetermined bias potential (e.g., about 3 V) to the transistors 4 and 5 during read access. The transistors 4 and 5 are set to have a threshold voltage of about 1.5 V including a substrate bias effect so that they operate to clamp a bit line potential at a voltage of about 1.5 V. The potential is clamped as described above to prevent soft write access during long-time read of the main memory cell 1. The dummy cell bias circuit 16 has the same arrangement as that of the bias circuit 6, and the dummy cell transistors 14 and 15 clamp a dummy cell bit line potential at a voltage of about 1.5 V as in the operation of the transistors 4 and 5. In the circuit of FIG. 1, a single-ended sense amplifying scheme in which a readout potential from the main memory cell 1 is input to the sense amplifier 20 and compared with a reference potential (a readout potential from the dummy cell 11) is used. In addition, a two-stage sense scheme in which the readout potential from the main memory cell 1 is amplified by the bit line transfer gate transistor 5 and then input to the sense amplifier 20 is also used.
An operation of the circuit in FIG. 1 will be described below. When the main memory cell 1 is set in a programmed state (OFF state), the potential of the bit line 2 goes to high level when the column selection transistor 3 is set in an ON state. In this example, the high level is 1.5 V. In contrast to this, when the main memory cell 1 is set in an erase state (ON state), the potential of the bit line 2 goes to low level when the column selection transistor 3 is set in an ON state. This low level can be set to be 1.2 V when the sizes of the bit line charge transistor 4 and the bit line transfer gate transistor 5 are adjusted. Therefore, the bit line potential can fall within an amplitude of about 0.3 V. In addition, when the threshold voltage of the bit line load transistor 7 is -1 V, the potential of the sense line 8 goes to 4 V when the bit line potential is set at high level (1.5 V). When the size of the bit line load transistor 7 is adjusted, the potential of the sense line 8 can be set to be, e.g., 3 V when the bit line potential is set at low level (1.2 V). That is, the small amplitude (0.3 V) of the bit line 2 is amplified to 1 V. A circuit scheme for amplifying the small amplitude of a bit line potential by the transfer gate transistor 5 and the load transistor 7 is to be referred to as a level shift circuit scheme hereinafter.
In this case, the sizes of the dummy cell 11, the dummy cell column selection transistor 13, the bit line charge transistor 14, and the dummy bit line transfer gate transistor 15 are set to be equal to the sizes of the main memory cell 1, the main memory cell column selection transistor 3, the bit line charge transistor 4, and the bit line transfer gate transistor 5, respectively. Therefore, when the dummy cell 11 is set in an erase state, and the power source potential Vcc is applied to the control gate of the dummy cell 11, currents having the same magnitude flow in the bit line charge transistor 4 and the dummy cell bit line charge transistor 14 when the selected main memory cell 1 is set in an erase state. The size of the dummy cell bit line load transistor 17 is set to be larger than that of the main memory cell bit line load transistor 7, and the conductance of the dummy cell bit line load transistor 17 is set to be higher than that of the main memory cell bit line load transistor 7. In this case, the potential of the dummy cell sense line 18 is higher than the low level of the main memory cell sense line 8. At the same time, when the conductance of the dummy cell bit line load transistor 17 is adjusted, the potential of the dummy cell sense line 18 can be set to be lower than the high level of the main memory cell sense line 8 (the potential is set at an intermediate level between the low and high levels of the main memory cell sense line 8). Therefore, when the potentials of the main memory cell sense line 8 and the dummy cell sense line 18 are compared with each other and amplified by the sense amplifier 20, it can be determined whether the main memory cell 1 is set in a programmed state.
Conventionally, in an SRAM (static memory) or a DRAM (dynamic memory), a high-speed read operation is achieved by a technique for equalizing the potentials of a pair of complementary bit lines. A pulse signal (equalizing signal) used for this equalization is supplied from an external circuit or generated by an internal circuit (address transition detector) in which transition of an address signal input is detected to generate a signal having a predetermined pulse width. Consequently, in the circuit of FIG. 1, a high-speed read operation is expected to be achieved by equalizing the potentials of the bit line 2 and the dummy cell bit line 12 or the potentials of the sense line 8 and the dummy cell sense line 18.
There is an attempt to apply the above equalization technique to the circuit in FIG. 1. A typical example of this attempt is made by W. Ip et al., "256 Kb CMOS EPROM" February 1984, ISSCC DIGEST OF TECHNICAL PAPERS, pp. 138-139, (FIG. 3), or H. Nakai et al. "A 36 ns 1M bit CMOS EPROM with new data sensing technique" Symposium on VLSI Circuits, pp. 95-96, 1990 (FIG. 1). In the former, only the potentials of a bit line and a dummy cell bit line are equalized. In the latter, only the potentials of a sense line and a dummy cell sense line are equalized. However, there is no literature describing that the potentials of a bit line and a dummy cell bit line and the potentials of a sense line and a dummy cell sense line are simultaneously equalized, because conditions for equalizing the potentials of the bit line and the dummy cell bit line cannot be preferably matched with conditions for equalizing the potentials of the sense line and the dummy cell sense line. In addition, in the circuit of FIG. 1, when a read current (to be referred to as a cell current hereinafter) when the main memory cell 1 is turned on is decreased, a switching speed of the main memory cell 1 is rapidly decreased, and a read rate largely depends on the cell current.
As described above, in a read circuit of two-stage sense system using a level shift circuit and a single-ended sense amplifier and frequently applied to a conventional nonvolatile semiconductor memory, the potentials of the bit line and the dummy cell bit line or the potentials of the sense line and the dummy cell sense line are not equalized. For this reason, a high-speed read operation is not sufficiently achieved, and a read rate largely depends on a cell current.